Results
- Showing results for:
- Reset all filters
Search results
-
Journal articleZaaimi B, Turnbull M, Hazra A, et al., 2023,
Closed-loop optogenetic control of the dynamics of neural activity in non-human primates
, NATURE BIOMEDICAL ENGINEERING, ISSN: 2157-846X- Author Web Link
- Cite
- Citations: 3
-
Conference paperTeversham J, Wong SS, Hsieh B, et al., 2022,
Development of an ultra low-cost SSVEP-based BCI device for real-time on-device decoding
, 2022 44th Annual International Conference of the IEEE Engineering in Medicine & Biology Society (EMBC), Publisher: IEEE, Pages: 208-213, ISSN: 2694-0604This study details the development of a novel, approx. £20 electroencephalogram (EEG)-based brain-computer interface (BCI) intended to offer a financially and operationally accessible device that can be deployed on a mass scale to facilitate education and public engagement in the domain of EEG sensing and neurotechnologies. Real-time decoding of steady-state visual evoked potentials (SSVEPs) is achieved using variations of the widely-used canonical correlation analysis (CCA) algorithm: multi-set CCA and generalised CCA. All BCI functionality is executed on board an inexpensive ESP32 microcontroller. SSVEP decoding accuracy of 95.56 ± 3.74% with an ITR of 102 bits/min was achieved with modest calibration.
-
Journal articleLauteslager T, Tommer M, Lande TS, et al., 2022,
Dynamic Microwave Imaging of the Cardiovascular System Using Ultra-Wideband Radar-on-Chip Devices
, IEEE TRANSACTIONS ON BIOMEDICAL ENGINEERING, Vol: 69, Pages: 2935-2946, ISSN: 0018-9294- Author Web Link
- Cite
- Citations: 2
-
Journal articleRapeaux A, Syed O, Cuttaz E, et al., 2022,
Preparation of rat sciatic nerve for ex vivo neurophysiology
, Jove-Journal of Visualized Experiments, Vol: 185, Pages: 1-14, ISSN: 1940-087XEx vivo preparations enable the study of many neurophysiological processes in isolation from the rest of the body while preserving local tissue structure. This work describes the preparation of rat sciatic nerves for ex vivo neurophysiology, including buffer preparation, animal procedures, equipment setup and neurophysiological recording. This work provides an overview of the different types of experiments possible with this method. The outlined method aims to provide 6 h of stimulation and recording on extracted peripheral nerve tissue in tightly controlled conditions for optimal consistency in results. Results obtained using this method are A-fibre compound action potentials (CAP) with peak-to-peak amplitudes in the millivolt range over the entire duration of the experiment. CAP amplitudes and shapes are consistent and reliable, making them useful to test and compare new electrodes to existing models, or the effects of interventions on the tissue, such as the use of chemicals, surgical alterations, or neuromodulatory stimulation techniques. Both conventional commercially available cuff electrodes with platinum-iridium contacts and custom-made conductive elastomer electrodes were tested and gave similar results in terms of nerve stimulus strength-duration response.
-
Journal articleZhang Z, Constandinou TG, 2022,
Selecting an effective amplitude threshold for neural spike detection.
, Annu Int Conf IEEE Eng Med Biol Soc, Vol: 2022, Pages: 2328-2331This paper assesses and challenges whether commonly used methods for defining amplitude thresholds for spike detection are optimal. This is achieved through empirical testing of single amplitude thresholds across multiple recordings of varying SNR levels. Our results suggest that the most widely used noise-statistics-driven threshold can suffer from parameter deviation in different noise levels. The spike-noise-driven threshold can be an ideal approach to set the threshold for spike detection, which suffers less from the parameter deviation and is robust to sub-optimal settings.
-
Journal articleOprea A, Zhang Z, Constandinou TG, 2022,
Hardware evaluation of spike detection algorithms towards wireless brain machine interfaces
<jats:title>Abstract</jats:title><jats:p>The current trend for implantable Brain Machine Interfaces (BMIs) is to increase the channel count, towards next generation devices that improve on information transfer rate. This however increases the raw data bandwidth for wired or wireless systems that ultimately impacts the power budget (and thermal dissipation). On-implant feature extraction and/or compression are therefore becoming essential to reduce the data rate, however the processing power is of concern. One common feature extraction technique for intracortical BMIs is spike detection. In this work, we have empirically compared the performance, resource utilization, and power consumption of three hardware efficient spike emphasizers, Non-linear Energy Operator (NEO), Amplitude Slope Operator (ASO) and Energy of Derivative (ED), and two common statistical thresholding mechanisms (using mean or median). We also propose a novel median approximation to address the issue of the median operator not being hardware-efficient to implement. These have all been implemented and evaluated on reconfigurable hardware (FPGA) to estimate their hardware efficiency in an ultimate ASIC design. Our results suggest that ED with average thresholding provides the most hardware efficient (low power/resource) choice, while using median has the advantage of improved detection accuracy and higher robustness on threshold multiplier settings. This work is significant because it is the first to implement and compare the hardware and algorithm trade-offs that have to be made before translating the algorithms into hardware instances to design wireless implantable BMIs.</jats:p>
-
Journal articleRapeaux A, Constandinou T, 2022,
HFAC dose repetition and accumulation leads to progressively longer block carryover effect in rat sciatic nerve
, Frontiers in Neuroscience, Vol: 16, ISSN: 1662-453XThis paper describes high-frequency nerve block experiments carried out on rat sciatic nerves to measure the speed of recoveryof A fibres from block carryover. Block carryover is the process by which nerve excitability remains suppressed temporarily afterHigh Frequency Alternative (HFAC) block is turned off following its application. In this series of experiments 5 rat sciatic nerveswere extracted and prepared for ex-vivo stimulation and recording in a specially designed perfusion chamber. For each nerverepeated HFAC block and concurrent stimulation trials were carried out to observe block carryover after signal shutoff. The nervewas allowed to recover fully between each trial. Time to recovery from block was measured by monitoring for when relativenerve activity returned to within 90% of baseline levels measured at the start of each trial. HFAC block carryover duration wasfound to be dependent on accumulated dose by statistical test for two different HFAC durations. The carryover property of HFACblock on A fibres could enable selective stimulation of autonomic nerve fibres such as C fibres for the duration of carryover. Blockcarryover is particularly relevant to potential chronic clinical applications of block as it reduces power requirements forstimulation to provide the blocking effect. This work characterises this process towards the creation of a model describing itsbehaviour.
-
Journal articleZamora M, Toth R, Morgante F, et al., 2022,
DyNeuMo Mk-1: Design and pilot validation of an investigational motion-adaptive neurostimulator with integrated chronotherapy
, EXPERIMENTAL NEUROLOGY, Vol: 351, ISSN: 0014-4886- Author Web Link
- Cite
- Citations: 11
-
Journal articleSavolainen OW, Zhang Z, Feng P, et al., 2022,
Hardware-Efficient Compression of Neural Multi-Unit Activity
<jats:title>Abstract</jats:title><jats:p>Brain-machine interfaces (BMI) are tools for treating neurological disorders and motor-impairments. It is essential that the next generation of intracortical BMIs is wireless so as to remove percutaneous connections, i.e. wires, and the associated mechanical and infection risks. This is required for the effective translation of BMIs into clinical applications and is one of the remaining bottlenecks. However, due to cortical tissue thermal dissipation safety limits, the on-implant power consumption must be strictly limited. Therefore, both the neural signal processing and wireless communication power should be minimal, while the implants should provide signals that offer high behavioural decoding performance (BDP). The Multi-Unit Activity (MUA) signal is the most common signal in modern BMIs. However, with an ever-increasing channel count, the raw data bandwidth is becoming prohibitively high due to the associated communication power exceeding the safety limits. Data compression is therefore required. To meet this need, this work developed hardware-efficient static Huffman compression schemes for MUA data. Our final system reduced the bandwidth to 27 bps/channel, compared to the standard MUA rate of 1 kbps/channel. This compression is over an order of magnitude more than has been achieved before, while using only 0.96 uW/channel processing power and 246 logic cells. Our results were verified on 3 datasets and less than 1% loss in BDP was observed. As such, with the use of effective data compression, an order more of MUA channels can be fitted on-implant, enabling the next generation of high-performance wireless intracortical BMIs.</jats:p>
-
Journal articleAhmadi N, Adiono T, Purwarianti A, et al., 2022,
Improved spike-based brain-machine interface using bayesian adaptive kernel smoother and deep learning
, IEEE Access, Vol: 10, Pages: 29341-29356, ISSN: 2169-3536Multiunit activity (MUA) has been proposed to mitigate the robustness issue faced by single-unit activity (SUA)-based brain-machine interfaces (BMIs). Most MUA-based BMIs still employ a binning method for estimating firing rates and linear decoder for decoding behavioural parameters. The limitations of binning and linear decoder lead to suboptimal performance of MUA-based BMIs. To address this issue, we propose a method which consists of Bayesian adaptive kernel smoother (BAKS) as the firing rate estimation algorithm and deep learning, particularly quasi-recurrent neural network (QRNN), as the decoding algorithm. We evaluated the proposed method for reconstructing (offline) hand kinematics from intracortical neural data chronically recorded from the primary motor cortex of two non-human primates. Extensive empirical results across recording sessions and subjects showed that the proposed method consistently outperforms other combinations of firing rate estimation algorithm and decoding algorithm. Overall results suggest the effectiveness of the proposed method for improving the decoding performance of MUA-based BMIs.
-
Journal articleZhang Z, Savolainen OW, Constandinou TG, 2022,
Algorithm and hardware considerations for real-time neural signal on-implant processing
, JOURNAL OF NEURAL ENGINEERING, Vol: 19, ISSN: 1741-2560- Author Web Link
- Cite
- Citations: 4
-
Journal articleZhang Z, Constandinou TG, 2022,
Selecting an effective amplitude threshold for neural spike detection
<jats:title>Abstract</jats:title><jats:p>This paper assesses and challenges whether commonly used methods for defining amplitude thresholds for spike detection are optimal. This is achieved through empirical testing of single amplitude thresholds across multiple recordings of varying SNR levels. Our results suggest that the most widely used noise-statistics-driven threshold can suffer from parameter deviation in different noise levels. The spike-noise-driven threshold can be an ideal approach to set the threshold for spike detection, which suffers less from the parameter deviation and is robust to sub-optimal settings.</jats:p>
-
Conference paperManatchinapisit V, Rapeaux A, Williams I, et al., 2022,
Accelerated testing of electrode degradation for validation of new implantable neural interfaces
, Pages: 534-538Neural prostheses, such as cochlear implants or deep brain stimulators, can modulate neural activity and restore lost physiological function by performing electrical stimulation and neural recordings. However, prolonged stimulation can degrade electrodes and adversely affect their performance over long-term implantation. Therefore, integrating the electrodes' health monitoring system is required for new implantable neural interface designs. However, validating the electrode degradation monitoring system with in-vivo experiment is slow and highly challenging. Furthermore, artificially generating the degradation of electrodes in in-vitro analysis is also time-consuming. This paper proposes an experimental setup for accelerated electrode degradation by elevating temperature and electrical stimulation. In order to demonstrate feasibility, a previous generation electrode material (tungsten) was used, and Electrochemical Impedance Spectroscopy (EIS) was measured every hour to analyse the electrochemical properties. As a result, optical microscopy images, before and after testing, show the morphology changes of the tungsten wire electrodes. The minimum accelerated testing to create electrode failure was 6 hours. Following prolonged stimulation, the results show electrode erosion possibly exacerbated by the evolution of hydrogen gas, while the EIS plots illustrate the slight increase of impedance over time in certain frequency bands, likely due to the progressive decline of the electrode surface area.
-
Conference paperJaccottet A, Feng P, Szostak-Lipowicz KM, et al., 2022,
Towards a wireless micropackaged implant with hermeticity monitoring
, Pages: 500-504The development of reliable hermetic chip-scale micropackaging is one of the major challenges in the miniaturization of implantable medical devices. Protecting the patient from the implanted foreign body and the implant itself from the biological environment is crucial. This paper presents an implantable micropackaging concept to protect a microelectronic system-on-chip. A hermetic chamber is formed by bonding the active CMOS chip to a silicon cover using a gold-tin eutectic sealant. The cover's fabrication method and the die's post-processing steps are presented. A humidity sensor inside the chamber monitors the humidity to assess permeability. To power the sensor and read its data, interconnections in the CMOS chip have been designed; these metal tracks pass underneath the cover and thus create a connection between the inside and the outside of the cavity. As an alternative to these connections, an on-chip wireless power management and data communication system is presented with simulated results.
-
Conference paperOprea A, Zhang Z, Constandinou TG, 2022,
Hardware evaluation of spike detection algorithms towards wireless brain machine interfaces
, Pages: 60-64The current trend for implantable Brain Machine Interfaces (BMIs) is to increase the channel count, towards next generation devices that improve on information transfer rate. This however increases the raw data bandwidth for wired or wireless systems that ultimately impacts the power budget (and thermal dissipation). On-implant feature extraction and/or compression are therefore becoming essential to reduce the data rate, however the processing power is of concern. One common feature extraction technique for intracortical BMIs is spike detection. In this work, we have empirically compared the performance, resource utilization, and power consumption of three hardware efficient spike emphasizers: Non-linear Energy Operator (NEO), Amplitude Slope Operator (ASO) and Energy of Derivative (ED), and two common statistical thresholding mechanisms (using mean or median). We also propose a novel median approximation to address the issue of the median operator not being hardware-efficient to implement. These have all been implemented and evaluated on reconfigurable hardware (FPGA) to estimate their hardware efficiency in an ultimate ASIC design. Our results suggest that ED with average thresholding provides the most hardware efficient (low power/resource) choice, while using median has the advantage of improved detection accuracy and higher robustness on threshold multiplier settings. This work is significant because it is the first to implement and compare the hardware and algorithm trade-offs that have to be made before translating the algorithms into hardware instances to design wireless implantable BMIs.
-
Conference paperStanchieri GDP, De Marcellis A, Faccio M, et al., 2022,
A 180 nm CMOS Integrated System based on a Multilevel Synchronized Pulsed Modulation for High Efficiency Implantable Optical Biotelemetry
, Pages: 302-306This paper reports on the design of a fully integrated UWB-inspired optical biotelemetry system for high efficiency implantable devices in biomedical applications. The communication link implements a multilevel data coding combined to a synchronized pulse position modulation technique operating with serial bitstreams having data rates from 60 Mbps to 240 Mbps and symbols composed by 1 up to 6 bits (configurable operating modes). The optical biotelemetry system takes advantage of the use of 300 ps laser pulses as the data transmitter and of a Si photodiode as the data receiver so guaranteeing reliable operations, wide bandwidth, high efficiency, electromagnetic compatibility, and signal integrity. The proposed system has been designed in TSMC 180 nm standard CMOS technology requiring a total Si area of about 0.044 mm2. Post-layout simulations demonstrate the correctness of the system functionalities and operations for transmission data rates up to 240 Mbps, symbol lengths up to 6 bits, and overall energy efficiencies lower than 22 pJ/bit. The comparison with results of similar solutions in the Literature demonstrates that the proposed system achieves the best performances in terms of data rate and energy efficiency.
-
Journal articleAntoniadis D, Mifsud A, Feng P, et al., 2022,
An Open-Source RRAM Compiler
, 2022 20TH IEEE INTERREGIONAL NEWCAS CONFERENCE (NEWCAS), Pages: 465-469 -
Journal articleRapeaux AB, Constandinou TG, 2021,
Implantable brain machine interfaces: first-in-human studies, technology challenges and trends
, CURRENT OPINION IN BIOTECHNOLOGY, Vol: 72, Pages: 102-111, ISSN: 0958-1669- Author Web Link
- Cite
- Citations: 27
-
Journal articleMaheshwari S, Stathopoulos S, Wang J, et al., 2021,
Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps
, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4862-4875, ISSN: 1549-8328Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
-
Journal articleMaheshwari S, Stathopoulos S, Wang J, et al., 2021,
Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout
, IEEE Transactions on Circuits and Systems I: Regular Papers, Vol: 68, Pages: 4876-4888, ISSN: 1549-8328\normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
This data is extracted from the Web of Science and reproduced under a licence from Thomson Reuters. You may not copy or re-distribute this data in whole or in part without the written consent of the Science business of Thomson Reuters.