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@inproceedings{Sundarasaradula:2017:10.1109/ICECS.2016.7841123,
author = {Sundarasaradula, Y and Constandinou, TG and Thanachayanont, A},
doi = {10.1109/ICECS.2016.7841123},
pages = {25--28},
publisher = {IEEE},
title = {A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications},
url = {http://dx.doi.org/10.1109/ICECS.2016.7841123},
year = {2017}
}

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TY  - CPAPER
AB  - This paper presents the design and realization of a novel low-power 6-bit successive approximation logarithmic ADC for biomedical applications. A two-step successive approximation method is proposed to obtain a piecewise-linear approximation of the desired logarithmic transfer function. The proposed ADC has been designed and simulated using process parameters from a standard 0.35 μm 2P4M CMOS technology with a single 1.8 V power supply voltage. Simulation results show that, at a sampling rate of 25 kS/s, the proposed ADC consumes 4.36 μW to 14.6 μW (proportional to input amplitudes). The proposed ADC achieves 18.6 pJ/conversion-step, maximum INL of 0.45 LSB, an ENOB of 4.97-bits, and SNDR of 31.7 dB with 1 V full-scale input range.
AU  - Sundarasaradula,Y
AU  - Constandinou,TG
AU  - Thanachayanont,A
DO  - 10.1109/ICECS.2016.7841123
EP  - 28
PB  - IEEE
PY  - 2017///
SP  - 25
TI  - A 6-bit, two-step, successive approximation logarithmic ADC for biomedical applications
UR  - http://dx.doi.org/10.1109/ICECS.2016.7841123
UR  - http://hdl.handle.net/10044/1/44156
ER  -

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