In this section
@inproceedings{Barsakcioglu:2016:10.1109/ISCAS.2016.7527489,
author = {Barsakcioglu, DY and Constandinou, TG},
doi = {10.1109/ISCAS.2016.7527489},
pages = {1310--1313},
publisher = {IEEE},
title = {A 32-Channel MCU-Based Feature Extraction and Classification for Scalable on-Node Spike Sorting},
url = {http://dx.doi.org/10.1109/ISCAS.2016.7527489},
year = {2016}
}
TY - CPAPER
AB - This paper describes a new hardware-efficientmethod and implementation for neural spike sorting basedon selection of a channel-specific near-optimal subset of fea-tures given a larger predefined set. For each channel, real-time classification is achieved using a simple decision matrixthat considers the features that provide the highest separabilitydetermined through off-line training. A 32-channel system for on-line feature extraction and classification has been implementedin an ARM Cortex-M0+ processor. Measured results of thehardware platform consumes 268 W per channel during spikesorting (includes detection). The proposed method provides atleast x10 reduction in computational requirements compared toliterature, while achieving an average classification error of lessthan 10% across wide range of datasets and noise levels.
AU - Barsakcioglu,DY
AU - Constandinou,TG
DO - 10.1109/ISCAS.2016.7527489
EP - 1313
PB - IEEE
PY - 2016///
SP - 1310
TI - A 32-Channel MCU-Based Feature Extraction and Classification for Scalable on-Node Spike Sorting
UR - http://dx.doi.org/10.1109/ISCAS.2016.7527489
UR - http://hdl.handle.net/10044/1/30123
ER -
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