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@article{Maheshwari:2021:10.1109/tcsi.2021.3122343,
author = {Maheshwari, S and Stathopoulos, S and Wang, J and Serb, A and Pan, Y and Mifsud, A and Leene, LB and Shen, J and Papavassiliou, C and Constandinou, TG and Prodromakis, T},
doi = {10.1109/tcsi.2021.3122343},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
pages = {4862--4875},
title = {Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps},
url = {http://dx.doi.org/10.1109/tcsi.2021.3122343},
volume = {68},
year = {2021}
}

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TY  - JOUR
AB  - Memristive technology has experienced explosive growth in the last decade, with multiple device structures being developed for a wide range of applications. However, transitioning the technology from the lab into the marketplace requires the development of an accessible and user-friendly design flow, supported by an industry-grade toolchain. In this work, we demonstrate the behaviour of our in-house fabricated custom memristor model and its integration into the Cadence Electronic Design Automation (EDA) tools for verification. Various input stimuli were given to record the memristive device characteristics both at the device level as well as the schematic level for verification of the memristor model. This design flow from device to industrial level EDA tools is the first step before the model can be used and integrated with Complementary Metal-Oxide Semiconductor (CMOS) in applications for hybrid memristor/CMOS system design.
AU  - Maheshwari,S
AU  - Stathopoulos,S
AU  - Wang,J
AU  - Serb,A
AU  - Pan,Y
AU  - Mifsud,A
AU  - Leene,LB
AU  - Shen,J
AU  - Papavassiliou,C
AU  - Constandinou,TG
AU  - Prodromakis,T
DO  - 10.1109/tcsi.2021.3122343
EP  - 4875
PY  - 2021///
SN  - 1549-8328
SP  - 4862
TI  - Design flow for hybrid CMOS/memristor systems--Part I: modeling and verification steps
T2  - IEEE Transactions on Circuits and Systems I: Regular Papers
UR  - http://dx.doi.org/10.1109/tcsi.2021.3122343
UR  - https://ieeexplore.ieee.org/document/9598176
UR  - http://hdl.handle.net/10044/1/92726
VL  - 68
ER  -

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