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@article{Maheshwari:2021:10.1109/tcsi.2021.3122381,
author = {Maheshwari, S and Stathopoulos, S and Wang, J and Serb, A and Pan, Y and Mifsud, A and Leene, LB and Shen, J and Papavassiliou, C and Constandinou, TG and Prodromakis, T},
doi = {10.1109/tcsi.2021.3122381},
journal = {IEEE Transactions on Circuits and Systems I: Regular Papers},
pages = {4876--4888},
title = {Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout},
url = {http://dx.doi.org/10.1109/tcsi.2021.3122381},
volume = {68},
year = {2021}
}

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TY  - JOUR
AB  - \normalsize The capability of in-memory computation, reconfigurability, low power operation as well as multistate operation of the memristive device deems them a suitable candidate for designing electronic circuits with a broad range of applications. Besides, the integrability of memristor with CMOS enables it to use in logic circuits too. In this work, we demonstrate with examples the design flow for memristor-based electronics, after the custom memristor model already being integrated and validated into our chosen Computer-Aided Design (CAD) tool to performing layout-versus-schematic and post-layout checks including the memristive device. We envisage that this step-by-step guide to introducing memristor into the standard integrated circuit design flow will be a useful reference document for both device developers who wish to benchmark their technologies and circuit designers who wish to experiment with memristive-enhanced systems.
AU  - Maheshwari,S
AU  - Stathopoulos,S
AU  - Wang,J
AU  - Serb,A
AU  - Pan,Y
AU  - Mifsud,A
AU  - Leene,LB
AU  - Shen,J
AU  - Papavassiliou,C
AU  - Constandinou,TG
AU  - Prodromakis,T
DO  - 10.1109/tcsi.2021.3122381
EP  - 4888
PY  - 2021///
SN  - 1549-8328
SP  - 4876
TI  - Design flow for hybrid CMOS/memristor systems--Part II: circuit schematics and layout
T2  - IEEE Transactions on Circuits and Systems I: Regular Papers
UR  - http://dx.doi.org/10.1109/tcsi.2021.3122381
UR  - https://ieeexplore.ieee.org/document/9598180
UR  - http://hdl.handle.net/10044/1/92725
VL  - 68
ER  -

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